Coherency probe with link or domain indicator
US9507715B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2014 |
| Grant date | Nov 29, 2016 |
| Priority date | — |
| Expiry date | Dec 31, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a set of processing modules, each of the processing modules including a cache and a coherency manager that keeps track of the memory addresses of data stored at the caches of other processing modules. In response to its local cache requesting access to a particular memory address or other triggering event, the coherency manager generates a coherency probe. In the event that the generated coherency probe is targeted to multiple processing modules, the coherency manager includes a set of multicast bits indicating the processing modules whose caches include copies of the data targeted by the multicast probe. A transport switch that connects the processing module to the fabric communicates the coherency probe only to subset of processing modules indicated by the multicast bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.