Patent · US Active

Identification of mistimed forcing of values in design simulation

US9507898B2 · kind B2 · utility

0Cited by
5References
9Claims
0Family size

Assignee

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Key dates

Filing dateDec 6, 2013
Grant dateNov 29, 2016
Priority date
Expiry dateOct 20, 2034

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F2119/12
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A computer identifies a storage element in a simulation model of an integrated circuit design that, during simulation of the integrated circuit design using the simulation model, is subject to having its value forced. In response to identifying the storage element, an indication of the storage element and the associated clock signal are stored in a database. In response to receiving an input indicating the value of the storage element is to be forced during simulation, a determination is made by reference to the database whether or not forcing of the value is mistimed with reference to the associated clock signal. In response to a determination that the forcing of the value as indicated by the input is mistimed with reference to the associated clock signal, an indication that forcing of the value is mistimed is output.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.