Method and circuit to enable wide supply voltage difference in multi-supply memory
US9508405B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2013 |
| Grant date | Nov 29, 2016 |
| Priority date | — |
| Expiry date | Feb 15, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for operating a memory device with wider difference in array and periphery voltage is presented. The memory device includes a bit line, a complementary bit line, a memory cell, a first pre-charge circuit, and a second pre-charge circuit. The memory cell, the first pre-charge circuit, and the second pre-charge circuit are coupled between the bit line and the complementary bit line. The first pre-charge circuit is configured to pre-charge the bit line and the complementary bit line to a first voltage level. The second pre-charge circuit is configured to pre-charge the bit line and the complementary bit line to a second voltage level that is different than the first voltage level. In some examples, two precharge circuits are configured to operate such that memory access is ensured to be static noise margin safe even under wider difference between two voltage levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.