Patent · US Active

Wiring configuration of a bus system and power wires in a memory chip

US9508407B2 · kind B2 · utility

1Cited by

10References

13Claims

0Family size

Assignee

Micron Technology, Inc. · US

Inventors

Maksim Kuzmenka · Birkenfeld, DE
Dirk Scheideler · Munich, DE
Kai Schiller · Munich, DE

Key dates

Filing date	May 9, 2014
Grant date	Nov 29, 2016
Priority date	—
Expiry date	May 18, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/4097
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Devices and circuits for wiring configurations of a bus system and power supply wires in a memory chip with improved power efficiencies. The effective resistance on the power supply wires may be reduced by utilizing non-active bus wires as additional power wires connected in parallel with the other supply wires. The non-active bus wires may reduce or prevent parasitic couplings and cross-talk effects between neighboring sensitive wires, thereby improving performance of the chip.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.