Semiconductor memory device and operation method thereof
US9508454B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2015 |
| Grant date | Nov 29, 2016 |
| Priority date | — |
| Expiry date | Aug 6, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are a semiconductor memory device and an operation method thereof. The semiconductor memory device includes a main buffer suitable for storing input data during a first operation period of a write operation, a repair operation unit suitable for selectively latching the input data based on whether the input data is used for repair during the first operation period of the write operation; a repair buffer suitable for storing the latched input data during a second operation period subsequent to the first operation period, and a column operation unit suitable for controlling an operation to write the input data stored in the main buffer or the repair buffer in a main memory cell or a repair memory cell during the second operation period of the write operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.