Method to form silicide and contact at embedded epitaxial facet
US9508601B2 · kind B2 · utility
0Cited by
6References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2014 |
| Grant date | Nov 29, 2016 |
| Priority date | — |
| Expiry date | Dec 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76897
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.