Chip package assembly and manufacturing method thereof
US9508677B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2016 |
| Grant date | Nov 29, 2016 |
| Priority date | — |
| Expiry date | Feb 23, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30101
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a chip package assembly can include: a first substrate at a bottom layer, the first substrate having a first surface and a second surface opposite to the first surface, where the second surface is provided with a first group of inner leads; at least one chip layer above the first group of inner leads, where each of the chip layers comprises a third surface and a fourth surface opposite to the third surface, where electrodes on the third surface that that lie at the lowest level are electrically coupled to the first group of inner leads through a first connector; and a second substrate above the fourth surface on the topmost layer and having a fifth surface, and where the fifth surface is provided with a second group of inner leads electrically coupled to the electrodes on the fourth surface on the topmost layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.