System and method for power management
US9513662B2 · kind B2 · utility
5Cited by
0References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2013 |
| Grant date | Dec 6, 2016 |
| Priority date | — |
| Expiry date | Mar 29, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.