Tamper detection arrangement for integrated circuits
US9514308B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 11, 2014 |
| Grant date | Dec 6, 2016 |
| Priority date | — |
| Expiry date | Apr 1, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A tamper detection arrangement for use within an integrated circuit (1), the arrangement comprising: at least one input capacitor (4) having a first capacitance value; a feedback capacitor (5) having a second capacitance value; a sensing arrangement comprising an amplifier circuit having the at least one input capacitor as an input and the at least one feedback capacitor in a feedback loop across the amplifier operable to detect a change in the capacitance values between the at least one input capacitor and the feedback capacitor; and a protective shield to protect a sensitive area (2) of the integrated circuit from tampering, the shield being provided by the at least one input capacitor (4).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.