Magnetic storage cell memory with back hop-prevention
US9514796B1 · kind B1 · utility
1Cited by
4References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 26, 2015 |
| Grant date | Dec 6, 2016 |
| Priority date | — |
| Expiry date | Jun 26, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1697
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.