Variable resistance memory device
US9514807B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2015 |
| Grant date | Dec 6, 2016 |
| Priority date | — |
| Expiry date | Dec 1, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A variable resistance memory device includes upper interconnections on a substrate, first and second word lines provided between the substrate and the upper interconnections and vertically spaced apart from each other, a first bit line disposed between the first and second word lines and intersecting the first and second word lines, memory cells provided in an intersecting region of the first word line and the first bit line and an intersecting region of the second word line and the first bit line, a first word line contact directly connecting the first word line to a corresponding one of the upper interconnections, and a second word line contact directly connecting the second word line to a corresponding one of the upper interconnections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.