Memristor using parallel asymmetrical transistors having shared floating gate and diode
US9514818B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2016 |
| Grant date | Dec 6, 2016 |
| Priority date | — |
| Expiry date | May 4, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A two-terminal, single-poly floating gate memristor includes parallel-connected, asymmetrical readout and injection transistors having a shared floating gate structure, and a diode connected to drain terminals of the asymmetrical transistors. The injection transistor is configured with relatively high source/drain-to-gate capacitances to facilitate EEPROM-type (floating gate) program/erase operations (e.g., hot carrier injection and band-to-band tunneling of holes), and the readout transistor is configured (e.g., using a threshold voltage implant) to facilitate low-voltage readout operations. The diode is configured to function both as a limiting resistor that prevents over-erase during high-voltage erase operations, and also to prevent sneak (leakage) currents during low-voltage readout operations. The diode is implemented using either p-n junction or Schottky diode configurations formed on bulk silicon, or a lateral diode configurations disclosed for SOI substrates. A memory circuit including multiple two-terminal memristors disposed in a cross-point array is disclosed, which can be utilized, e.g., in a neuromorphic circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.