Patent · US Active

Electroless metal through silicon via

US9514985B2 · kind B2 · utility

3Cited by

3References

6Claims

0Family size

Assignee

SILEX MICROSYSTEMS AB · SE

Inventors

Thorbjörn Ebefors · Huddinge, SE
Henrik Knutsson · Binstead Close, SE

Key dates

Filing date	Sep 27, 2013
Grant date	Dec 6, 2016
Priority date	—
Expiry date	Sep 27, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/10253
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method of making a substrate-through metal via having a high aspect ratio, in a semiconductor substrate, and a metal pattern on the substrate surface, includes providing a semiconductor substrate (wafer) and depositing poly-silicon on the substrate. The poly-silicon on the substrate surface is patterned by etching away unwanted portions. Then, Ni is selectively deposited on the poly-silicon by an electroless process. A via hole is made through the substrate, wherein the walls in the hole is subjected to the same processing as above. Cu is deposited on the Ni by a plating process. Line widths and spacings <10 μm are provided on both sides of the wafer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.