Semiconductor devices having isolation insulating layers and methods of manufacturing the same
US9515172B2 · kind B2 · utility
14Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 20, 2015 |
| Grant date | Dec 6, 2016 |
| Priority date | — |
| Expiry date | Jan 20, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The inventive concepts provide semiconductor devices and methods of manufacturing the same. Semiconductor devices of the inventive concepts may include a fin region comprising a first fin subregion and a second fin subregion separated and isolated from each other by an isolation insulating layer disposed therebetween, a first gate intersecting the first fin subregion, a second gate intersecting the second fin subregion, and a third gate intersecting the isolation insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.