Methods of manufacturing semiconductor devices using cavities to distribute conductive patterning residue
US9515255B2 · kind B2 · utility
1Cited by
1References
18Claims
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Key dates
| Filing date | Oct 24, 2014 |
| Grant date | Dec 6, 2016 |
| Priority date | — |
| Expiry date | Oct 24, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods of manufacturing a semiconductor device include forming a conductive layer on a substrate, forming an air gap or other cavity between the conductive layer and the substrate, and patterning the conductive layer to expose the air gap. The methods may further include forming conductive pillars between the substrate and the conductive layer. The air gap may be positioned between the conductive pillars.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.