Automatically placed-and-routed ADPLL with PWM-based DCO resolution enhancement
US9515668B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2014 |
| Grant date | Dec 6, 2016 |
| Priority date | — |
| Expiry date | May 31, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An all digital phase-locked loop (PLL) and a method of controlling the PLL is provided. The method includes the steps of receiving a reference signal (fREF) at a controller and a time-to-digital converter (TDC), the controller and TDC being coupled to multiple tunable delay elements; receiving at the multiple tunable delay elements a first signal input via the controller and a pulse-width modulation (PWM) circuit; providing an PLL output (fDCO) to the TDC at least partially based on the first signal input; and generating a phase error output (ΦERR) based on the reference signal (fREF) and the PLL output (fDCO), wherein the phase error output (ΦERR) is provided as feedback to the controller to control the PLL output (fDCO).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.