Muhammad Faisal
17Patents
4h-index
16Co-inventors
53Inventor score
Filing activity: May 31, 2014 → Sep 20, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US11798298B2 | Distracted driving detection using a multi-task training process | Physics | 25 | Active |
| US11532169B1 | Distracted driving detection using a multi-task training process | Physics | 25 | Active |
| US9641183B2 | Dual-loop programmable and dividerless clock generator for ultra low power applications | Electricity | 7 | Active |
| US9762249B1 | Reconfigurable phase-locked loop | Electricity | 4 | Active |
| US9680480B1 | Fractional and reconfigurable digital phase-locked loop | Electricity | 3 | Active |
| US9705516B1 | Reconfigurable phase-locked loop with optional LC oscillator capability | Electricity | 3 | Active |
| US9515668B2 | Automatically placed-and-routed ADPLL with PWM-based DCO resolution enhancement | Electricity | 1 | Active |
| US11720790B2 | Method of training image deep learning model and device thereof | Physics | 0 | Active |
| US12062243B2 | Distracted driving detection using a multi-task training process | Physics | 0 | Active |
| US10614182B2 | Timing analysis for electronic design automation of parallel multi-state driver circuits | Physics | 0 | Active |
| US10031992B2 | Concurrently optimized system-on-chip implementation with automatic synthesis and integration | Physics | 0 | Active |
| US10740526B2 | Integrated circuit design system with automatic timing margin reduction | Emerging Cross-Sectional Technologies | 0 | Active |
| US11989927B2 | Apparatus and method for detecting keypoint based on deep learning using information change across receptive fields | Physics | 0 | Active |
| US10587275B2 | Locked loop circuit with configurable second error input | Electricity | 0 | Active |
| US10158365B2 | Digital, reconfigurable frequency and delay generator with phase measurement | Electricity | 0 | Active |
| US10713409B2 | Integrated circuit design system with automatic timing margin reduction | Emerging Cross-Sectional Technologies | 0 | Active |
| US11017138B2 | Timing analysis for parallel multi-state driver circuits | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.