High-speed dequeuing of buffer IDS in frame storing system
US9515946B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 1, 2014 |
| Grant date | Dec 6, 2016 |
| Priority date | — |
| Expiry date | Mar 19, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/622
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Incoming frame data is stored in a plurality of dual linked lists of buffers in a pipelined memory. The dual linked lists of buffers are maintained by a link manager. The link manager maintains, for each dual linked list of buffers, a first head pointer, a second head pointer, a first tail pointer, a second tail pointer, a head pointer active bit, and a tail pointer active bit. The first head and tail pointers are used to maintain the first linked list of the dual linked list. The second head and tail pointers are used to maintain the second linked list of the dual linked list. Due to the pipelined nature of the memory, the dual linked list system can be popped to supply dequeued values at a sustained rate of more than one value per the read access latency time of the pipelined memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.