Voltage contrast characterization structures and methods for within chip process variation characterization
US9519210B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2014 |
| Grant date | Dec 13, 2016 |
| Priority date | — |
| Expiry date | Jan 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for designing, a structure, method of inspecting and a computer system for designing voltage contrast integrated circuit characterization. The design method includes selecting a design level of a mask design shapes file; selecting a region of the design level having an open region having no design shapes and an adjacent circuit region having circuit design shapes; selecting a sub-region of the circuit region adjacent to the open region; copying design shapes of the sub-region to generate a characterization cell identical to the sub-region; modifying the characterization cell to generate a passive voltage contrast characterization cell; and placing the passive voltage contrast characterization cell into the open region adjacent to the sub-region to generate a modified design level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.