Method and apparatus for power throttling of highspeed multi-lane serial links
US9519331B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2013 |
| Grant date | Dec 13, 2016 |
| Priority date | — |
| Expiry date | Oct 11, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for managing the power consumption of an information handling system including a multi-lane serial link having a lane setting that identifies the number of active lanes in the multi-lane serial link. The method may include determining a number of lanes required for the multi-lane serial link based on one or more I/O devices connected to the information handling system, triggering a reduction of the lane setting of the multi-lane serial link if the lane setting of the multi-lane serial link is greater than the determined number of lanes required, and automatically reducing power to the multi-lane serial link in response to the reduction of the lane setting.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.