Error recovery following speculative execution with an instruction processing pipeline
US9519538B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2011 |
| Grant date | Dec 13, 2016 |
| Priority date | — |
| Expiry date | Aug 9, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0721
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction processing pipeline having error detection and error recovery circuitry associated with one or more of the pipeline stages. If an error is detected within a signal value within that pipeline stage, then it can be repaired. Part of the error recovery may be to flush upstream program instructions from the instruction pipeline. When multi-threading, only those instructions from a thread including an instruction which has been lost as a consequence of the error recovery need be flushed from the instruction pipeline. The instruction pipeline may additionally/alternatively be provided with more than one main storage element associated with each signal value with these main storage elements used in an alternating fashion such that if a signal value has been erroneously captured and needs to be repaired, there is still available a main storage element to properly capture the signal value corresponding to the following program instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.