Electronic device
US9520186B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2014 |
| Grant date | Dec 13, 2016 |
| Priority date | — |
| Expiry date | Aug 8, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory may include: a first stacked structure including a first word line disposed over a substrate and extended in a first direction, a first bit line disposed over the first word line and extended in a second direction crossing the first direction, and a first variable resistance layer interposed between the first word line and the first bit line; and a second stacked structure including a second bit line disposed over the first stacked structure and extended in the second direction, a second word line disposed over the second bit line and extended in the first direction, and a second variable resistance layer interposed between the second word line and the second bit line; and a first selecting element layer interposed between the first bit line and the second bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.