Adaptive erase of a storage device
US9520197B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2013 |
| Grant date | Dec 13, 2016 |
| Priority date | — |
| Expiry date | Nov 8, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/349
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The various implementations described herein include systems, methods and/or devices used to enable adaptive erasure in a storage device. The method includes performing a plurality of memory operations including read operations and respective erase operations on portions of one or more non-volatile memory devices specified by the read operations and respective erase operations, where the respective erase operations are performed using a first set of erase parameters that has been established as a current set of erase parameters prior to performing the respective erase operations. The method includes, in accordance with each erase operation of at least a subset of the respective erase operations, updating one or more erase statistics that correspond to performance of multiple erase operations. The method includes, in accordance with a comparison of the erase statistics with an erasure performance threshold, establishing a second set of erase parameters as the current set of erase parameters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.