Semiconductor device having interconnect layer that includes dielectric segments interleaved with metal components
US9520362B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2015 |
| Grant date | Dec 13, 2016 |
| Priority date | — |
| Expiry date | May 7, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.