Vertical gate-all-around field effect transistors and methods of forming same
US9520466B2 · kind B2 · utility
118Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2015 |
| Grant date | Dec 13, 2016 |
| Priority date | — |
| Expiry date | Mar 16, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices and methods of forming the same are provided. A template layer is formed on a substrate, the template layer having a recess therein. A plurality of nanowires is formed in the recess. A gate stack is formed over the substrate, the gate stack surrounding the plurality of nanowires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.