Power gating and clock gating in wiring levels
US9520876B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2016 |
| Grant date | Dec 13, 2016 |
| Priority date | — |
| Expiry date | Feb 17, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/522
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor comprising a front end of line portion including a logical processing unit (LPU) and a second LPU. The first LPU configured to perform a first operation and the second LPU configured to perform a second operation following the first operation. A back end of line portion including a plurality of wiring levels, and further including a power gate and a clock gate that are integrated into one or more wiring levels of the plurality of wiring levels. The power gate and clock gate are further electrically connected to the first LPU by an enable wire. The power gate and clock gate are electrically connected to a power grid and a clock net, respectively, by the enable wire, and the enable wire is further electrically connected to a latch of the second LPU. A signal wire is electrically connected to the first LPU and to the latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.