Computer processor employing hardware-based pointer processing
US9524163B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2014 |
| Grant date | Dec 20, 2016 |
| Priority date | — |
| Expiry date | Apr 4, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer processor is provided with execution logic that performs operations that utilize pointers stored in memory. In one aspect, each pointer is associated with a predefined number of event bits. The execution logic processes the event bits of a given pointer in conjunction with processing a predefined pointer-related operation involving the given pointer in order to selectively output an event-of-interest signal.In another aspect, each pointer is represented by an address field and a granularity field. The address field includes a chunk address and an offset. The granularity field represents granularity of the offset of the address field. The execution logic includes an address derivation unit that processes the granularity field of a base address for a given pointer in order to generate a valid address field for the derived pointer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.