Apparatuses and methods for generating a suppressed address trace
US9524227B2 · kind B2 · utility
1Cited by
5References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2014 |
| Grant date | Dec 20, 2016 |
| Priority date | — |
| Expiry date | Jan 27, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3656
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses for generating a suppressed address trace are described. In some embodiments, a processor includes a trace generator having a trace suppressor that outputs a suppressed address trace for instructions executed by the processor. In some embodiments, a method to generate a suppressed address trace for a processor includes generating a suppressed address trace of executed instructions from a trace suppressor of a trace generator of the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.