Cache memory system with simultaneous read-write in single cycle
US9524242B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2014 |
| Grant date | Dec 20, 2016 |
| Priority date | — |
| Expiry date | Dec 28, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache includes a number of cache ways each having tag memory fields and corresponding data fields. With a simultaneous read-write operation defined by a read memory address (read tag portion and read index portion) and a write memory address (write tag portion and write index portion), the cache determines a read cache hit and reads from one cache way as indicated by the read tag and index portions of the read memory address. Furthermore, a determination is made as to whether a write as indicated by the write tag and index portions of the write memory address would be made in a same one cache way as the read so as to be in conflict. If such a conflict exists, the write is instead effectuated, simultaneously with the read to the one cache way, to a different cache way than is used for the read.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.