DRAM sub-array level autonomic refresh memory controller optimization
US9524771B2 · kind B2 · utility
9Cited by
4References
21Claims
0Family size
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Key dates
| Filing date | Jan 6, 2014 |
| Grant date | Dec 20, 2016 |
| Priority date | — |
| Expiry date | Mar 22, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/40611
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of refreshing a dynamic random access memory (DRAM) includes detecting an open page of the DRAM at a row of a DRAM bank within an open sub-array of the DRAM bank. The method also includes delaying issuance of a refresh command to a target refresh row of the DRAM bank when the target refresh row of the DRAM bank is within the open sub-array of the DRAM bank.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.