Semiconductor device comprising an e-fuse and a FET
US9524962B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2013 |
| Grant date | Dec 20, 2016 |
| Priority date | — |
| Expiry date | Dec 20, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device including the steps of forming an electrically programmable fuse (e-fuse) on an isolation region and a transistor on an active region of a wafer, wherein forming the transistor includes forming a dummy gate above a substrate, removing the dummy gate and forming a metal gate in place of the dummy gate, and forming the e-fuse includes forming a metal-containing layer above the isolation region, forming a semiconductor layer on the metal-containing layer during the process of forming the dummy gate and of the same material as the dummy gate, forming a hard mask layer on the semiconductor layer formed on the metal-containing layer, and forming contact openings in the hard mask layer and semiconductor layer during the process of removing the dummy gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.