Metal layers for a three-port bit cell
US9524972B2 · kind B2 · utility
6Cited by
12References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2015 |
| Grant date | Dec 20, 2016 |
| Priority date | — |
| Expiry date | Feb 12, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a first metal layer coupled to a bit cell. The apparatus also includes a third metal layer including a write word line that is coupled to the bit cell. The apparatus further includes a second metal layer between the first metal layer and the third metal layer. The second metal layer includes two read word lines coupled to the bit cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.