Memory device using graphene as charge-trap layer and method of operating the same
US9525076B2 · kind B2 · utility
1Cited by
3References
6Claims
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Key dates
| Filing date | Aug 6, 2013 |
| Grant date | Dec 20, 2016 |
| Priority date | — |
| Expiry date | Sep 11, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/938
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A graphene memory includes a source and a drain spaced apart from each other on a conductive semiconductor substrate, a graphene layer contacting the conductive semiconductor substrate and spaced apart from and between the source and the drain, and a gate electrode on the graphene layer. A Schottky barrier is formed between the conductive semiconductor substrate and the graphene layer such that the graphene layer is used as a charge-trap layer for storing charges.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.