Packages for semiconductor devices and methods for assembling same
US9527727B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 26, 2014 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Sep 26, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
One or more embodiments of the present disclosure are directed to packages that include a stacked microelectromechanical sensor MEMS die and an application-specific integrated circuit (ASIC) die. The smaller of the MEMS die and the ASIC die is stacked on the larger of the MEMS die and the ASIC die. The larger of the two dice may form one or more dimensions of the package. In one embodiment, a bottom surface of the larger of the two dice forms an outer surface of the package. In that regard, the package may take less lateral space on another component, such as a board or other package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.