Integrated circuit package and method
US9527728B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jul 22, 2013 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Aug 19, 2033 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C2203/0154
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method of forming a packaged electronic device includes fabricating a MEMS structure, such as a BAW structure, on a first semiconductor wafer substrate; forming a cavity in a second semiconductor wafer substrate; and mounting the second substrate on the first substrate such that the MEMS structure is positioned inside the cavity in the second substrate. A wafer level assembly and an integrated circuit package are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.