Methods for cache line eviction
US9529730B2 · kind B2 · utility
3Cited by
3References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2014 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Jan 20, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1041
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for evicting cache lines from a cache memory includes receiving a request from one of a plurality of processors. The cache memory is configured to store a plurality of cache lines, and a given cache line includes an identifier indicating a processor that performed a most recent access of the given cache line. The method further includes selecting a cache line for eviction from a group of least recently used cache lines, where each cache line of the group of least recently used cache lines occupy a priority position less that a predetermined value, and then evicting the selected cache line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.