Performance estimation using configurable hardware emulation
US9529946B1 · kind B1 · utility
10Cited by
15References
14Claims
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Key dates
| Filing date | Nov 13, 2012 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Mar 10, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit can include a processor operable to execute program code and an Intellectual Property (IP) modeling block. The IP modeling block can include a first port through which the IP modeling block receives first modeling data and a second port coupled to the processor through which the first IP modeling block communicates with the processor during emulation. The first IP modeling block also can include a power emulation circuit. The power emulation circuit is configured to consume a variable amount of power as specified by the first modeling data received via the first port.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.