Minimizing crossover paths for functional verification of a circuit description
US9529948B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2014 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Feb 7, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for functional verification of a circuit description comprises generating a first set of crossover paths based on the circuit description, generating a low power information based on a power design description associated with the circuit description, the low power information determining a set of power state combinations, and generating a second set of crossover paths based on the first set of crossover paths and the low power information, the second set of crossover paths being a subset of the first set of crossover paths. Each of the second set of crossover paths is evaluated to identify circuit description errors, in particular functional circuit description errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.