Methods, apparatus and system determining dual port DC contention margin
US9530488B1 · kind B1 · utility
3Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2016 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Feb 19, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
At least one method, apparatus and system disclosed involves testing a dual port memory cell in a memory device. A semiconductor wafer is processed for providing a dual port memory device. An inline DC contention margin test is performed for testing a contention margin related to a write operation into a cell of the memory device. A determination is made as to whether the contention margin is within a predetermined range. A responsive action is performed in response to determining that the contention margin is outside the predetermined range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.