Protective trench layer and gate spacer in finFET devices
US9530665B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2014 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Aug 13, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Forming a field effect transistor device includes forming first and second semiconductor fins on a semiconductor substrate. The first and second semiconductor fins are separated by a trench region. The trench region has a first sidewall corresponding to a sidewall of the first semiconductor fin and a second sidewall corresponding to a sidewall of the second semiconductor fin. A gate stack is arranged over respective channel regions of the first and semiconductor fins. A first sidewall of the gate stack corresponds to a third sidewall of the trench region. A protective layer is formed only on a bottom portion of the trench region and along the first sidewall of the gate stack. The protective layer along the first sidewall of the gate stack defines a gate spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.