Image sensor integrated circuit package with reduced thickness
US9530818B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 27, 2014 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Sep 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/12043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An image sensor die may include a pixel array formed in an image sensor substrate. The image sensor die may be mounted to a thin metal interconnect layer that has been deposited on a sacrificial carrier substrate. The thin metal interconnect layer may include one or more metal layers that are patterned to form metal traces that serve as contact pads, signal lines, and other interconnects in the interconnect layer. The image sensor die may be wire bonded, flip-chip mounted, or otherwise mechanically and electrically coupled to the metal interconnect layer. The sacrificial carrier substrate may be etched or otherwise removed to expose the metal interconnects on the metal interconnect layer. An array of solder balls may be formed on the exposed metal interconnects to form a ball grid array package, or the exposed contact pads may be plated to form a leadless chip carrier package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.