Monolithic three dimensional memory arrays with staggered vertical bit line select transistors and methods therfor
US9530824B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2014 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Apr 10, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A monolithic three-dimensional memory array is provided that includes a plurality of global bit lines disposed above a substrate, each global bit line having a long axis, a plurality of vertically-oriented bit lines disposed above the global bit lines, a plurality of word lines disposed above the global bit lines, a plurality of memory cells coupled between the vertically-oriented bit lines and the word lines, and a plurality of vertically-oriented bit line select transistors coupled between the vertically-oriented bit lines and the global bit lines, each vertically-oriented bit line select transistor comprising a width and a thickness. Vertically-oriented bit line select transistors disposed above adjacent global bit lines are offset from one another in a direction along the long axis of the global bit lines. The width of each vertically-oriented bit line select transistor is greater than the thickness of the vertically-oriented bit line select transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.