Frequency scaled segmented scan chain for integrated circuits
US9535123B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2015 |
| Grant date | Jan 3, 2017 |
| Priority date | — |
| Expiry date | Dec 31, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318575
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A scan chain may be formed throughout an integrated circuit in which the scan chain includes at least a first segment and a second segment. A first portion of a test pattern is scanned into the first segment by clocking a first scan cell of the first segment with an even clock while clocking a remainder of the plurality of scan cells in the first segment with an odd clock, in which the odd clock is out of phase with the even clock, in which the even clock and odd clock have a rate equal to a scan rate of the test pattern divided by an integer N. A second portion of the test pattern is scanned into the second segment by clocking the plurality of scan cells in the second segment with the odd clock, such that the second portion of the test pattern is not scanned into the first segment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.