Wilson Pradeep
20Patents
3h-index
14Co-inventors
52Inventor score
Filing activity: Dec 31, 2015 → Mar 13, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10184980B2 | Multiple input signature register analysis for digital circuitry | Physics | 5 | Active |
| US10579454B2 | Delay fault testing of pseudo static controls | Physics | 4 | Active |
| US11604221B1 | Clock shaper circuit for transition fault testing | Physics | 3 | Active |
| US9535123B2 | Frequency scaled segmented scan chain for integrated circuits | Physics | 3 | Active |
| US10331826B2 | False path timing exception handler circuit | Electricity | 2 | Active |
| US11073557B2 | Phase controlled codec block scan of a partitioned circuit device | Physics | 2 | Active |
| US11333707B2 | Testing of integrated circuits during at-speed mode of operation | Physics | 2 | Active |
| US11209481B2 | Multiple input signature register analysis for digital circuitry | Physics | 1 | Active |
| US10776546B2 | False path timing exception handler circuit | Electricity | 1 | Active |
| US11073553B2 | Dynamic generation of ATPG mode signals for testing multipath memory circuit | Physics | 1 | Active |
| US11194645B2 | Delay fault testing of pseudo static controls | Physics | 0 | Active |
| US11519964B2 | Phase controlled codec block scan of a partitioned circuit device | Physics | 0 | Active |
| US11680984B1 | Control data registers for scan testing | Physics | 0 | Active |
| US11194944B2 | False path timing exception handler circuit | Electricity | 0 | Active |
| US12216160B2 | Clock shaper circuit for transition fault testing | Physics | 0 | Active |
| US10473717B2 | Methods and apparatus for test insertion points | Physics | 0 | Active |
| US11047910B2 | Path based controls for ATE mode testing of multicell memory circuit | Physics | 0 | Active |
| US11768726B2 | Delay fault testing of pseudo static controls | Physics | 0 | Active |
| US11879940B2 | Dynamic generation of ATPG mode signals for testing multipath memory circuit | Physics | 0 | Active |
| US11933844B2 | Path based controls for ATE mode testing of multicell memory circuit | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.