Conditional operation in an internal processor of a memory device
US9535876B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 4, 2009 |
| Grant date | Jan 3, 2017 |
| Priority date | — |
| Expiry date | Mar 8, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An internal processor of a memory device configured to selectively execute instructions in parallel. One such internal processor includes a plurality of arithmetic logic units (ALUs), each connected to conditional masking logic, and each configured to process conditional instructions. A condition instruction may be received by a sequencer of the memory device. Once the condition instruction is received, the sequencer may enable the conditional masking logic of the ALUs. The sequencer may toggle a signal to the conditional masking logic such that the masking logic masks certain instructions if a condition of the condition instruction has been met, and masks other instructions if the condition has not been met. In one embodiment, each ALU in the internal processor may selectively perform instructions in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.