Gap fill self planarization on post EPI
US9536771B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2013 |
| Grant date | Jan 3, 2017 |
| Priority date | — |
| Expiry date | Apr 23, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to an integrated chip IC having transistors with structures separated by a flowable dielectric material, and a related method of formation. In some embodiments, an integrated chip has a semiconductor substrate and an embedded silicon germanium (SiGe) region extending as a positive relief from a location within the semiconductor substrate to a position above the semiconductor substrate. A first gate structure is located at a position that is separated from the embedded SiGe region by a first gap. A flowable dielectric material is disposed between the gate structure and the embedded SiGe region and a pre-metal dielectric (PMD) layer disposed above the flowable dielectric material. The flowable dielectric material provides for good gap fill capabilities that mitigate void formation during gap fill between the adjacent gate structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.