Semiconductor device and method of fabricating the same
US9536897B2 · kind B2 · utility
26Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2015 |
| Grant date | Jan 3, 2017 |
| Priority date | — |
| Expiry date | Apr 24, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
Abstract
A three-dimensional semiconductor device may include a substrate including a cell array region, a word line contact region, and a peripheral circuit region, gate electrodes stacked on the substrate to extend from the cell array region to the word line contact region, a channel hole penetrating the gate electrodes on the cell array region and exposing an active region of the substrate, a dummy hole penetrating the gate electrodes on the word line contact region and exposing a device isolation layer provided on the substrate, and a semiconductor pattern provided in the channel hole but not in the dummy hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.