Gate spacers and methods of forming same
US9536980B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2015 |
| Grant date | Jan 3, 2017 |
| Priority date | — |
| Expiry date | Jul 28, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment device includes a gate stack extending over a semiconductor substrate, a hard mask disposed on a top surface of the gate stack, and a low-k dielectric spacer on a side of the gate stack. A top of the low-k dielectric spacer is lower than an upper surface of the hard mask. The device further includes a contact electrically connected to a source/drain region adjacent the gate stack. The contact extends laterally over the low-k dielectric spacer, and a dielectric material is disposed between the contact and the low-k dielectric spacer. The dielectric material has a higher selectivity to etching than the low-k dielectric spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.