Semiconductor device with SiC base layer
US9537002B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2013 |
| Grant date | Jan 3, 2017 |
| Priority date | — |
| Expiry date | Mar 18, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/157
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A base layer is used that has an N-type SiC layer formed in a surface layer on the front surface side of an N-type SiC substrate, and a P-type region is formed on a surface of the N-type SiC layer with an N-type source region selectively formed in a surface layer of the P-type region. A source electrode is formed on a surface of the N-type source region and a drain electrode is formed on the back surface side of the N-type SiC substrate. Additionally, the gate electrode is formed via a gate insulation film only on a surface of the P-type region. In this way, high electric field is no longer applied to the gate insulation film on the surface of the N-type SiC layer due to stoppage of voltage application to the gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.