Memory device, gate stack and method for manufacturing the same
US9537016B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2016 |
| Grant date | Jan 3, 2017 |
| Priority date | — |
| Expiry date | Feb 3, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
Abstract
A memory device is disclosed. The memory device includes a substrate, including a substrate, including a source region and a drain region; and a gate stack, formed over a surface of the substrate, wherein the gate stack includes: a tunneling layer; a first layer; a second layer; a third layer; and a blocking layer; wherein each of the tunneling layer and the blocking layer has an oxygen proportion higher than the first, the second and the third layers; the first layer has a highest silicon proportion among the first, the second and the third layers; the second layer has a highest oxygen proportion among the first, the second and the third layers; and the first layer has a highest nitrogen proportion among the first, the second and the third layers. An associated gate stack and a manufacturing method are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.